1. Field of the Invention
The present invention relates to wafer-level packaging for a semiconductor die. More particularly, the present invention relates to a semiconductor die having all of its sides sealed by a passivation layer and an improved method for forming the passivation layers on the semiconductor die.
2. State of the Art
A solid-state electronic device in the form of a semiconductor die or chip is conventionally manufactured of materials such as silicon, germanium, or gallium arsenide. Circuitry is formed on an active surface of the semiconductor die and may include further levels of circuitry within the die itself. Bond pads are conventionally formed on the active surface to provide electrical contacts for the semiconductor die circuitry. Due to the materials used and the intricate nature of construction, semiconductor dice are highly susceptible to physical damage or contamination from environmental conditions including, for example, moisture.
Conventionally, attempts to protect a semiconductor die from environmental conditions have included mounting the die within a plastic, metal or ceramic package that provides hermetic sealing and prevents environmental elements from physically contacting the die. Such a package also conventionally includes conductive leads or similar conductive elements for attaching the die bond pads to external electrical connections. Such a packaging approach, while providing some protection for the semiconductor die from external conditions, increases the cost of production by requiring additional materials and manufacturing steps. Additionally, such a packaging approach results in a relatively large device size which may unnecessarily consume valuable real estate when mounted to a carrier substrate. Moreover, the conductive lead structures used in such packaging approaches may negatively influence processing speed and, further, may present opportunities for moisture incursion at interfaces between the conductive leads and other packaging materials.
There have been some efforts to reduce the size and cost of these electronic devices which have resulted in, more or less, doing away with the above-described packaging materials. Such efforts include, for example, fabrication processes commonly referred to as wafer-level packaging (WLP) or chip-scale packaging (CSP). Such packaging methods include disposing a relatively thin protective coating or passivation layer on one or more surfaces of the semiconductor die during fabrication. Connecting elements, such as conductive bumps, are formed over the die bond pads using a variety of known techniques such as screen printing or ball bumping. A redistribution layer may also be formed on the active surface of the semiconductor die to allow the formation of conductive bumps at locations other than directly above the bond pads. The conductive bumps may then be electrically connected to circuitry on a carrier substrate or other device through a process such as tape automated bonding (TAB), or by direct attachment including mounting the semiconductor die in a flip-chip fashion on the carrier substrate.
Formation of the passivation layer on the surfaces of the semiconductor die may include sealing exposed die surfaces with a coating of, for example, silicon nitride (SiN), silicon dioxide (SiO2), or other materials such as an epoxy or a polymer. In prior art processes, such coatings might be deposited on the active and passive surfaces of a wafer, which contains an array of solid-state electronic devices, with the wafer being subsequently singulated to provide individual semiconductor dice. The semiconductor dice which result from this fabrication process suffer from the fact that their side edges are left exposed after singulation of the dice from the wafer. The possibility remains, therefore, that moisture may enter the side edges of an individual die and damage nearby circuitry.
It is further noted that, when processes such as wafer-level packaging and chip-scale packaging are utilized, difficulties may arise in the dicing of the wafer to effect singulation of the semiconductor dice therefrom. Such dicing is conventionally accomplished by cutting the wafer along street lines between the individual semiconductor dice with a wafer saw. However, when a passivation layer or coating on the wafer is formed of a polymer or similar material, the wafer saw tends to gum-up during singulation, thereby reducing cutting efficiency and requiring down time for cleaning and maintenance of the saw.
In order to rectify some of these shortcomings, various attempts have been made to provide additional passivation layers on the side edges of a semiconductor die. For example, U.S. Pat. No. 5,451,550 to Wills et al., U.S. Pat. No. 5,742,094 to Ting and U.S. Pat. No. 5,933,713 to Farnworth teach methods of providing side edge passivation layers to semiconductor dice. While the methods disclosed by these patents provide such side edge passivation layers, they may require further processing of the semiconductor dice on an individual basis, which becomes time consuming, introduces additional expense, and may introduce additional complexities into the fabrication process.
Other attempts to improve WLP and CSP processes include, for instance, U.S. Pat. No. 5,956,605 to Akram et al. and U.S. Pat. No. 6,303,977 to Schroen et al., which generally contemplate forming side edge passivation layers after wafer singulation. However, such methods may still result in die surfaces which are not completely coated and may require additional coating steps subsequent to attachment of the semiconductor die to a carrier substrate or other device.
In view of the shortcomings in the art, it would be advantageous to provide an improved wafer-level packaging method for sealing the surfaces of a semiconductor die.